With increasingly smaller geometries and feature sizes of integrated circuit devices (chips), an ever-increasing amount of logic can be placed on a single chip. Semiconductor manufacturers are under increasing pressure to reduce the number of defective products shipped while producing large volumes at low costs. Semiconductor manufacturing tests can be expensive and time consuming. One method to decrease the cost of test while being able to ship large product volumes is to test multiple chips in parallel using multi-site test. Another method is to apply efficient and high-quality tests using a low cost tester that use very limited set of pins. In addition to wafer and module testing described above some other applications that will benefit from reliable and efficient low cost testing include burn-in test and system or board-test.
Chip customers in some design spaces would like to reduce the number of test pins down to three or fewer pins, for example in automotive applications or for analog chips have a small amount of digital logic. In these spaces, test pin access is very limited. These chip customers would like to have one input pin for test data, one output pin for test data, and one test clock.
However, such a low number of pins can negatively impact the quality of the results obtained from testing. Reduced pin counts require test data compression, whereby the test data is compressed from a larger number of pins down to a small number of pins. Even for a small number of pins, complete test generation programs are generally required. Such test generation programs generally include high test coverage, low tester volumes, memory self-test, logic self-test, on-product clock generation, and other mechanisms to verify that the design was manufactured correctly. Presently, to accomplish these requirements, more than three pins are required.
Furthermore, the power consumed during the run of the test application must fit within the power budget for the chip. Modern chips, such as a typical system-on-a-chip device, may have millions of flops, such that the power consumption from toggle activity from scan shifting during test may easily exceed the limits allowed by the power budget. Where a low-number of pins are used, present low-pin test methods do not allow for multiple controlled scan clocks that may be staggered to reduce instantaneous switching activity, and thus power consumption.
In light of the above, there is a need for a low-pin scanning architecture that enables a full test suite, provides good quality of results, and addresses scan power issues in a low-pin environment.